1;3409;0c Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors

Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors

36th annual international symposium on Computer architecture, 2009
Pages: 290-301DOI: 10.1145/1555754.1555792

ISCA

bibtex

With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computing systems. Many issues of parallelism management boil down to discerning which running threads or processes are critical, or slowest, versus which are non-critical. If one can accurately predict critical threads in a parallel program, then one can respond in a variety of ways. Possibilities include running the critical thread at a faster clock rate, performing load balancing techniques to offload work onto currently non-critical threads, or giving the critical thread more on-chip resources to execute faster.