Evaluating Associativity in CPU Caches
The authors present new and efficient algorithms for simulating alternative direct-mapped and set-associative caches and use them to quantify the effect of limited associativity on the cache miss ratio. They introduce an algorithm, forest simulation, for simulating alternative direct-mapped caches and generalize one, which they call all-associativity simulation, for simulating alternative direc
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Cache Memories
ACM Computing Surveys, vol. 14,no. 3,1982 – CSUR
Cache memories are used in modern, medium and high-speed CPUs to hold temporarily those portions of the contents of main memory which are {believed to be) currently in use. Since instructions and data in cache memories can usually be referenced in 10 ...
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Cache Performance of Operating System and Multiprogramming Workloads
ACM Transactions on Computer Systems, vol. 6,no. 4,1988 – TOCS
Large caches are necessary in current high-performance computer systems to provide the required high memory bandwidth. Because a small decrease in cache performance can result in significant system performance degradation, accurately characterizing ...
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ATUM: A New Technique for Capturing Address Traces Using Microcode
13th annual international symposium on Computer architecture, 1986 – ISCA
Trace-driven simulation is often used in the design of computer systems, especially caches and translation lookaside buffers. Capturing address traces to drive such simulations has been problematic, often involving 1000:1 software overhead to trace a ...
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ATUM: a new technique for capturing address traces using microcode
ACM SIGARCH Computer Architecture News, vol. 14,no. 2,1986 – CAN
Trace-driven simulation is often used in the design of computer systems, especially caches and translation lookaside buffers. Capturing address traces to drive such simulations has been problematic, often involving 1000:1 software overhead to trace a ...
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Cache Performance in the VAX-11/780
ACM Transactions on Computer Systems, vol. 1,no. 1,1983 – TOCS
in the VAX-11/780 The performance ofmemory caches is usuallystudied through trace-drivensimulation.This approach has several drawbacks. Notably, it excludes realistic multiprogramming, operating system, and I/O activity. In this paper, cache ...
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On the Inclusion Properties for Multi-Level Cache Hierarchies
15th Annual International Symposium on Computer architecture, 1988 – ISCA
The inclusion property is essential in reducing the cache coherence complexity for multiprocessors with multilevel cache hierarchies. We give some necessary and sufficient conditions for imposing the inclusion property for fully- and set-associative ...
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An Analytical Cache Model
ACM Transactions on Computer Systems, vol. 7,no. 2,1989 – TOCS
Trace-driven simulation and hardware measurement are the techniques most often used to obtain accurate performance figures for caches. The former requires a large amount of simulation time to evaluate each cache configuration while the latter is ...
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A Case for Direct-Mapped Caches
IEEE Computer, vol. 21,no. 12,1988 – MC
Direct-mapped caches are defined, and it is shown that trends toward larger cache sizes and faster hit times favor their use. The arguments are restricted initially to single-level caches in uniprocessors. They are then extended to two-level cache ...
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