Steve Scott
Cray
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Synchronization and communication in the T3E multiprocessor
ACM SIGPLAN Notices, vol. 31,no. 9,1996 – SIGPLAN_Notices
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have learned from the T3D project (the predecessor to the T3E) and the ...
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Synchronization and communication in the T3E multiprocessor
ACM SIGOPS Operating Systems Review, vol. 30,no. 5,1996 – SIGOPS
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have learned from the T3D project (the predecessor to the T3E) and the ...
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The BlackWidow High-Radix Clos Network
ACM SIGARCH Computer Architecture News, vol. 34,no. 2,2006 – CAN
This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32K processors with a worstcase diameter of seven hops, and the underlying high-radix ...
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Technology-Driven, Highly-Scalable Dragonfly Topology
ACM SIGARCH Computer Architecture News, vol. 36,no. 3,2008 – CAN
Evolving technology and increasing pin-bandwidth motivate the use of high-radix routers to reduce the diameter, latency, and cost of interconnection networks. High-radix networks, however, require longer cables than their low-radix counterparts. ...
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The BlackWidow High-Radix Clos Network
33rd annual international symposium on Computer Architecture, 2006 – ISCA
This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32K processors with a worstcase diameter of seven hops, and the underlying high-radix ...
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Performance of the CRAY T3E multiprocessor
1997 ACM/IEEE conference on Supercomputing, 1997 – SC
The CRAY T3E is a scalable shared-memory multiprocessor based on the DEC Alpha 21164 microprocessor. The system includes a number of architectural features designed to tolerate latency and enhance scalability. Included among these are stream buffers, ...
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Performance of the SCI ring
ACM SIGARCH Computer Architecture News, vol. 20,no. 2,1992 – CAN
The Scalable Coherent Interface (SCI) is an emerging IEEE standard that provides computer-bus-like services to a set of nodes via fast, unidirectional links. This paper presents the first detailed performance study of the SCI ring, using both ...
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Using feedback to control tree saturation in multistage interconnection networks
ACM SIGARCH Computer Architecture News, vol. 17,no. 3,1989 – CAN
In this paper, we propose the use of feedback schemes in multiprocessors which use an interconnection network with distributed routing control. We show that by altering system behavior so as to minimize the occurrence of a performance-degrading ...
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The Cray BlackWidow: a highly scalable vector multiprocessor
2007 ACM/IEEE Conference on Supercomputing, 2007 – SC
This paper describes the system architecture of the Cray BlackWidow scalable vector multiprocessor. The BlackWidow system is a distributed shared memory (DSM) architecture that is scalable to 32K processors, each with a 4-way dispatch scalar ...
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Technology-Driven, Highly-Scalable Dragonfly Topology
35th International Symposium on Computer Architecture (ISCA 2008), 2008 – ISCA
Evolving technology and increasing pin-bandwidth motivate the use of high-radix routers to reduce the diameter, latency, and cost of interconnection networks. High-radix networks, however, require longer cables than their low-radix counterparts. ...
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